This invention relates to a process for producing a printed circuit board by forming conductor circuits only by an electroless plating (hereinafter referred to as "a full additive process").
As processes for producing printed circuit boards by depositing metal films on circuit forming portions only by an electroless plating method, there is a so-called non-covering method as disclosed in U.S. Pat. No. 4,151,313 which comprises adhering a catalyst for the electroless plating to a whole surface of an insulating substrate, removing the catalyst from the surface except for portions on which circuits are to be formed, and forming circuits by electroless plating. According to this method, since the electroless plating is conducted after the removal of catalyst from the portions wherein no circuit is formed, that is, there is no complicated steps between the step of catalyst removal and the step of electroless plating, there is no problem of transfer of catalyst to the portions on which circuits are to be formed and printed circuit boards having high wiring accuracy without depositing the metal on the portions other than the circuit forming portions can be obtained. But this method has a problem in that high and complicated techniques are necessary for adhering the catalyst to only the circuit forming portions.
In order to solve such a problem, there is employed a so-called covering method (e.g., Japanese Patent Appln. Kokai (Laid-Open) No. 22841/80) comprising the following steps (a) to (e):
(a) forming an adhesive layer on a surface of substrate,
(b) roughening the surface of the adhesive layer by, for example, an acid treatment,
(c) depositing a catalyst for electroless plating on the roughened surface of the adhesive layer,
(d) masking portions other than circuit forming portions with a resist ink by means of, for example, a silk-screen printing method, and
(e) forming conductive circuits by electroless plating.
But according to the present inventors' investigation, it has been observed that there very often takes place a trouble of short circuits due to transfer of the catalyst on the circuit forming portions to the resist ink film surface and deposition of a plating film on said resist ink film surface, during the masking step (d) or the later step. The undesirable transfer of catalyst to the resist ink film surface is a problem specifically caused in the covering method comprising the steps (a) through (e) in this order as mentioned above and not caused in other methods disclosed, for example, in U.S. Pat. Nos. 3,546,011, 4,212,912 and 4,311,749. Reasons therefor are not clear. But, it can be estimated that the transfer of catalyst is caused by lowering of the catalyst holding ability of and adhesive layer by the surface roughening treatment with, for example, an acid, which makes the catalyst in the state of easily releasable and contact of the substrate surface with various machines and devices or with other treated substrate during the step of masking resist ink by printing, at a time of stocking before transporting to the step of plating, during the transportation of the substrate to the step of plating or the like. Therefore, removal of the trouble caused by the transfer of catalyst has long been desired.
On the other hand, there often take place blisters under the plating film, when a substrate containing a fire retardant, particularly that of a phosphorous series or a halogen series, is used. Therefore, the removal of such blisters has also long been desired.